Historic

Contributed 2 testcircuits and supported the creation of arrays. Developed at the University of Groningen. Paper: Leo, Gibertini et al., ISCAS 2026.

Mixed-signal neuromorphic processor (180 nm CMOS) built around on-chip learning: 180 adaptive-exponential integrate-and-fire neurons in two cores with ~9,000 plastic synapses running trace-based local STDP/SRDP. Designed as a research platform for back-end-of-line integration of memristive, beyond-CMOS synaptic devices. Developed at the University of Groningen. Papers: Greatorex, Richter et al., Nature Communications 2025; Greatorex, Cotteret et al., ICONS 2026.

Texel

Learning-oriented test chip with neurons in 1D arrays supporting two on-chip local learning rules (BCaLL and DPSS). Also carries several interface and bio-inspired test circuits, including a touch-sensor interface. Developed at the University of Groningen. Papers: Richter, Greatorex et al., ICONS 2023; Mastella, Greatorex et al., ICONS 2023; Cotteret, Richter et al., ISCAS 2023; Mastella, Greatorex et al., Asilomar 2024; Janotte, Bamford et al., NEWCAS 2022; Greatorex, Mastella et al., 2025, arXiv:2501.10155.

Cognigr1

Test chip for characterising ferroelectric (FeFET) synapses through direct-access synapse arrays, evaluating emerging non-volatile devices for in-memory synaptic weight storage. Developed at the University of Groningen.

2BeFerro

Fully event-driven vision SoC that co-integrates a 128×128 dynamic vision sensor with the DYNAP-CNN spiking-convolutional processor: up to ~0.32 M integrate-and-fire neurons across nine configurable sCNN layers with on-the-fly computed synapses (~1 MB on-chip memory), running always-on smart vision. Developed at SynSense AG. Papers: Richter, Xing et al., 2023, arXiv:2304.06793; Yao, Richter et al., Nature Communications 2024.

Speck1

Configurable mixed-signal spiking processor: 1024 analog adaptive integrate-and-fire neurons in 2×2 cores with 65k plastic synapses (AMPA/GABA/NMDA/SHUNT) and packet-switched axon routing, in 180 nm subthreshold CMOS. Emulates biological neuron and synapse dynamics in physical time at sub-mW power. Developed at SynSense AG and UZH / ETH Zurich. Paper: Richter, Wu et al., Neuromorphic Comput. Eng. 2024.

DynapSE2

Fully asynchronous, event-driven convolutional neuromorphic processor (22 nm, 12 mm²) with over 1 M spiking neurons and ~4 MB of on-chip memory for spiking CNNs. Interfaces directly to external event sensors for always-on, sub-5 ms vision at ultra-low power. Developed at SynSense AG. Paper: Liu, Richter et al., CVPR Workshops 2019.

DynapCNN