We build asynchronous integrated circuits - data and event-driven silicon — as well as mixed-signal and custom integartion with colaborators, and the design EDA tools that go with them. Our work spans the full stack, from custom circuit and cell libraries, memory to architecture and System-on-Chip alongside the EDA flow. Our chips are application focused and we are particualrly looking into smart sensing and hardware for miniture robotics.

Asynchronous IC design

Clockless, event-driven circuits and architectures. Removing the global clock enables data-driven activity, fine-grained power gating and robustness to variation — properties we exploit for energy efficiency and modularity.

Selected papers:

Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive Circuits — ASYNC 2026

Neuromorphic / bio-inspired AI hardware

Efficient, low-power bio-inspired neurosynaptic AI processor pipelines. We take inspiration from biological neural systems to build unconventional, highly efficient AI processors — spiking and mixed-signal architectures that push the efficiency boundary beyond conventional synchronous accelerators.

Selected papers:

A neuromorphic processor with on-chip learning for beyond-CMOS device integration — Nature Communications 2025
DYNAP-SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor — Neuromorphic Comput. Eng. 2024
A subthreshold second-order integration circuit for versatile synaptic alpha kernel and trace generation — ICONS 2023

Smart sensing & hardware for miniature robotics

Hardware for closed-loop robotics at small scale: smart sensors and event-driven processing co-designed with the actuation loop, where low power and low latency are decisive.

Selected papers:

Spike-based dynamic computing with asynchronous sensing-computing neuromorphic chip — Nature Communications 2024
Neuromorphic capacitive tactile sensors inspired by slowly adaptive mechanoreceptors — NEWCAS 2022
Live demonstration: face recognition on an ultra-low power event-driven CNN ASIC — CVPR Workshops 2019

EDA for asynchronous design

Asynchronous design is only practical with the right tools. We develop and extend EDA for async circuits — synthesis, verification and layout flows — much of it open source. See Software & Tools.

Selected papers:

Taking Timing Out of the Equation: Moving Fully Automated Synthesis as close as possible to Delay-Insensitive Circuits — ASYNC 2026
Open-source asynchronous periphery for mixed-signal neuromorphic chips — ICONS 2026

Research is realized in silicon: see the Chips we have taped out.